In some applications, the switching node of a boost converter (DC-DC converter) is used to drive an additional charge pump that is coupled to the switching node. Such a configuration is shown in FIG. 1. There is a power transistor MOS which is part of the DC-DC converter and controlled according to a boost converter regulation scheme. There is further an inductor L which is coupled between an input voltage VI (input voltage of the DC-DC converter) and the switching node SW. The charge pump basically includes a flying capacitor CFL, and three diodes D1, D2 and D3 as well as two buffer capacitors CBUF1 and CBUF2. The boost converter output BOOSTOUT is fed through diode D1 from switching node SW. This voltage is buffered with buffer capacitor CBUF1. The diodes D2 and D3 in combination with the flying capacitor CFL generate a higher output voltage at node CPOUT which is buffered on the other buffer capacitor CBUF2. Accordingly, the charge pump (basically CFL, D2, D3 and CBUF2) is configured to use the output voltage BOOSTOUT and the voltage at the switching pin SW of the boost converter for doubling the boost output voltage at node CPOUT. In a boost converter configuration having a current mode control mechanism, the current information is typically sensed during the ON-time of the power transistor MOS, either at the power transistor MOS itself or at a sense resistor (not shown) which is coupled in series with the power transistor. A standard peak current control topology is shown in FIG. 2. There is the low side power MOSFET MOS of the DC-DC boost converter. The power transistor MOS is coupled with its channel between the switching node SW and ground. A current information is sensed through the voltage drop of the power transistor MOS. This is performed by the sampling switch SW1 which is coupled between the switching node SW and the negative input VS of amplifier A2. The positive input of amplifier A2 receives a voltage that is derived from the output voltage VOUT of the DC-DC converter. There is a resistive divider R1, R2 coupled to the output node VOUT. The divided voltage FB is fed to the negative input of amplifier A1. The positive input receives a reference voltage VREF. The output of amplifier A1 is fed to the positive input of amplifier A2 as voltage VE (error voltage). A series of a resistor R3 and a capacitor C1 is also coupled to the positive input VE of amplifier A2. The output of amplifier A2 is coupled to the reset input R of an RS-flipflop FF. The set input S of the RS-flip-flop receives an oscillating clock signal from oscillator OSC. The output of RS-flipflop FF is coupled to the control gate of the power MOSFET MOS. The transistor MOS is turned off when the current through the channel of transistor MOS reaches a certain peak value which is determined by the output of the error amplifier A1. The power transistor MOS is then turned on again either by the oscillator OSC or an OFF-timer (not shown). However, if a charge pump is connected to the switching pin SW, an additional current may be injected to the flying capacitor CFL (shown in FIG. 1) which is connected to the power transistor MOS of the boost converter. This additional current may distort the current information of the boost converter and have an impact on the duty cycle. The smaller the duty cycle and the smaller the slope at node VS, the more the regulation may be disturbed due to the additional current being injected into the power transistor MOS. This can adversely affect the operation of the converter and the charge pump or even, dependent on the load of the charge pump and the duty cycle of the boost converter, the converter and the charge pump can become unstable.